IEEE

Design of Ternary Logic and Arithmetic Circuits Using GNRFET

Abstract: Multiple valued logic (MVL) can represent an exponentially higher number of data/information compared to the binary logic for the same number of logic bits. Compared to the conventional and ...
C&EN

Deoxyribozyme-Based Ligase Logic Gates and Their Initial Circuits

Division of Clinical Pharmacology and Experimental Therapeutics, Department of Medicine, Columbia University, Box 84, 630 West 168th Street, New York, New York 10032, and Department of Computer ...
Investing

QuickLogic receives orders for strategic radiation hardened FPGA dev kit

SAN JOSE, Calif. - QuickLogic Corporation (NASDAQ:QUIK) has received initial orders for its Strategic Radiation Hardened FPGA Development Kit, the company announced Wednesday. The small-cap technology ...
IEEE

A Logic Synthesis Methodology for Low-Power Ternary Logic Circuits

Abstract: We propose a logic synthesis methodology with a novel low-power circuit structure for ternary logic. The proposed methodology synthesizes a ternary function as a ternary logic gate using ...